1. Field of the Invention
The present invention relates generally to microprocessors, and more particularly, to microprocessor clock buffers.
2. Description of Related Art
Currently, most mainstream electronic components and systems, such as microprocessors, are synchronous systems employing one or more system clocks that act as the driving force or xe2x80x9cheartxe2x80x9d of the electronic system. As a result, more often than not, it is critical that a given system clock signal arrive at various points in the system at nearly the same time.
Conventionally, clock buffers are used to boost the clock signal for distribution throughout the clock network(s) in the microprocessor. Relatively speaking, clock buffers tend to cover a very large area of a microprocessor, both in terms of the physical size the clock buffer occupies on the microprocessor and the area its output wires cover.
FIG. 1 illustrates a schematic diagram of a microprocessor 102 having a clock network 100 including a clock buffer 110 found in the prior art. In FIG. 1, microprocessor 102 includes clock buffer 110 having parallel inverters 114-124 which boost a clock signal input to wire 112. Although six inverters are illustrated in the FIG. 1 for clarity of description, more typically, a greater number of inverters are utilized, such as sixteen or thirty-two inverters. In some devices, other amplifying devices are used rather than inverters, such as, for example, transistors, or banks of transistors or inverters.
For the purposes of timing analysis, it is convenient to assume that the entire drive strength, e.g., generated current, of clock buffer 110 can be output, or sourced, from a single source point 128 to clock network 100. This timing abstraction, termed point source modeling, is used for modeling the timing of the clock network signal at different network levels in the microprocessor but ignores that the actual drive strength is distributed over the physical area of clock buffer 110. This timing abstraction limits the accuracy at the next timing level and also limits the hardware performance of microprocessor 102 as described below.
In FIG. 1, each inverter 114-124 is internally coupled along a single wire 126, and outputs current onto wire 126. Due to the large current carried on wire 126, it is very wide. The current is then converged at a central source point 128 for output from clock buffer 110 to clock network 100. From source point 128, wires 130 and 132 further distribute the current to clock network 100, such as an H-tree network. Due to the large current carried on wires 130 and 132, they are also very wide.
Conventionally, wires, such as wires 126, 130 and 132, are routed on the metal layers of a microprocessor. Further, most semiconductor manufacturing processes and integrated circuit design teams typically route wires in one direction on each metal layer with adjacent metal layers routed orthogonal to each other. Thus, in order to route the current of clock network 100 in different directions, the current is routed from source point 128 of wire 126 to an adjacent metal layer or layers of microprocessor 102 containing differently directed wires 130 and 132.
In many clock networks, such as an H-tree network, this routing between adjacent metal layers is often accomplished using conductive vias. Typically, there is a large via array (not shown) at source point 128 for routing the current from wire 126 to wires 130 and 132 (on a different metal layer) for further distribution to clock network 100.
In terms of current, all of the drive strength is spread out over the width of clock buffer 110 as each of inverters 114-124 outputs current along the length of wire 126. Then, the current from each inverter 114-124 is internally converged at one central point, e.g., source point 128, before the current is routed back out over wires 130 and 132 for distribution to the much larger area of clock network 100, and sometimes in the direction from which the current originally came. Thus, all of the current from each half of the drive strength is transported over one wire, e.g., wire 126, for output from central source point 128 to clock network 100. For example, clock buffer 110 can be 300 microns wide, and the current from clock buffer 110 output to clock network 100 that is 2 millimetersxc3x972 millimeters in size. With this prior art technique, the current from outermost inverters 114 and 124 traverse approximately 150 microns on wire 126 to arrive at source point 128 before further distribution to clock network 100. Current from inverters 116-122, which are located closer to source point 128, traverse lesser distances dependent upon the position of the individual inverter 116-122 relative to source point 128.
This technique presents several disadvantages. First, the current output from the inverters 114-124 is initially spread out over the width of the clock buffer 110, and then the current is converged at central source point 128 before the current is spread out again and routed to clock network 100, sometimes resulting in the current being routed back over the direction from which the current originally came. This generates extra work and slows down the current, e.g., the clock signal.
Second, to carry the large current load, wires 126, 130, and 132 are very wide. From a manufacturing standpoint, wide metal wires don""t behave the same in the manufacturing process as narrow metal wires. In narrow metal wires, the oxide on the sides of the narrow metal wire provides support to the width of the metal during planarization processes, such that the narrow metal wire comes out square and rectangular. Whereas with wide metal wires, the oxide on the sides of the metal can""t provide enough support to the entire width of the metal, and thus dishing of the metal during manufacturing becomes a problem.
Third, the circuitry associated with wide metal wires is more difficult to design. For example, if a wire is narrow enough and the resistance is strong enough, inductance becomes a negligible factor in the design of the circuit. However, the wider the wire becomes, the more problematic the factor of inductance becomes in the circuit. Calculating the effect of inductance in this situation is a very complicated extraction and simulation problem requiring additional design time.
Fourth, wide wires use a larger amount of routable space in a microprocessor, and in many cases, there is seldom enough space between power rails in a microprocessor to fabricate a wide wire.
Fifth, it is very difficult to design the via array and wire mass associated with distribution of the current from source point 128 so that the current comes evenly through all the vias for distribution to the clock network. It is through the vias that all the current has to change from one direction to another, and often current crowding occurs. If there are a large number of vias in a via array, it is difficult to guarantee that they are all being used. Typically, current tends to utilize the vias at the edges of the via array rather than those in the center of the via array making it difficult to determine if the vias are electromigration clean.
According to the principles of this invention, there are provided devices, methods, and networks that divide and proportionally distribute the drive strength of a clock buffer such that the output drive strength of the clock buffer is divided proportionally among a plurality of outputs from the clock buffer.
According to one embodiment, a buffer device having an output drive strength includes: a plurality of amplifying devices; and a plurality of outputs conductively coupled to the plurality of amplifying devices such that the output drive strength of the buffer device is divided proportionally among the plurality of outputs. In some embodiments, the plurality of outputs are conductively coupled to the plurality of amplifying devices by a connector wire such that the output drive strength of the buffer device is divided proportionally among the plurality of outputs. In some embodiments, the connector wire is selectively coupled to at least one of a plurality of distribution wires, wherein each of the plurality of distribution wires conductively couples a first amplifying device and a second amplifying device of the plurality of amplifying devices, the first amplifying device being adjacent to the second amplifying device.
In another embodiment, a network includes: a buffer device having an output drive strength, the buffer device dividing and proportionally distributing the output drive strength for output over multiple outputs; a plurality of network segments coupled to at least some of the multiple outputs of the buffer device; and a plurality of wires coupling the at least some of the multiple outputs of the buffer device to the plurality of network segments, the plurality of wires being coupled to at least some of the multiple outputs of the buffer device such that the drive strength of the buffer device is proportionally distributed over the buffer device and output to the network segments.
In a further embodiment, a method for dividing and distributing the drive strength of a single clock buffer to a clock network includes: obtaining a plurality of parallel inverters, each of the plurality of parallel inverters generating an equal drive strength; internally coupling different adjacent pairs of the plurality of parallel inverters with a plurality of distribution wires, wherein each one of the plurality of distribution wires couples a different adjacent pair of the plurality of parallel inverters; internally coupling at least some of the plurality of distribution wires to at least some of a plurality of outputs, wherein each of the at least some of the plurality of outputs is coupled to a different distribution wire such that the output drive strength of the clock buffer is divided proportionally among the plurality of outputs; and coupling segments of a clock network to at least some of the plurality of outputs so that the drive strength of the clock buffer is proportionally distributed to the clock network. In some embodiments, the at least some of the plurality of distribution wires are internally coupled to the at least some of the plurality of outputs by a connector wire such that the output drive strength of the buffer device is divided proportionally among the at least some of the plurality of outputs.
As a result of these and other features discussed in more detail below, devices, methods, and networks designed according to the principles of the present invention allow more efficient distribution of clock signals to a clock network when compared to the prior art technique earlier described.
It is to be understood that both the foregoing general description and the following detailed description are intended only to exemplify and explain the invention as claimed.